Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point

US7810054B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Theodoros E. Anemikos · Colchester, US
• Jeanne P. Bickford · South Burlington, US
• Laura S. Chadwick · South Burlington, US
• Susan K. Lichtensteiger · South Burlington, US
• Anthony D. Polson · Jericho, US

Key dates

• Filing date: Mar 4, 2008
• Grant date: Oct 5, 2010
• Expiry date: Mar 3, 2029

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2119/06
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method of optimizing power usage in an integrated circuit design analyzes multiple operating speed cut points that are expected to be produced by the integrated circuit design. The operating speed cut points are used to divide identically designed integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast integrated circuit devices. The method selects an initial operating speed cut point to minimize a maximum power consumption level of the relatively slow integrated circuit devices and the relatively fast identically designed integrated circuit devices. The method then manufactures the integrated circuit devices using the integrated circuit design and tests operating speeds and power consumption levels of the identically designed integrated circuit devices. Then, the method adjusts the initial operating speed cut point to a final operating speed cut point based on the testing, to minimize the maximum power consumption level of the relatively slow integrated circuit devices and the relatively fast integrated circuit devices.