Method of controlling metal silicide formation
US7811877B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2007 |
| Grant date | Oct 12, 2010 |
| Priority date | — |
| Expiry date | Dec 28, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of processing silicon substrates to form metal silicide layers thereover having more uniform thicknesses are provided herein. In some embodiments, a method of processing a substrate includes providing a substrate having a plurality of exposed regions comprising silicon, wherein at least two of the plurality of exposed regions have a different rate of formation of a metal silicide layer thereover; doping at least one of the exposed regions to control the rate of formation of a metal silicide layer thereover; and forming a metal silicide layer upon the exposed regions of the substrate, wherein the metal silicide layer has a reduced maximum thickness differential between the exposed regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.