Designating operands with fewer bits in instruction code by indexing into destination register history table for each thread
US7814299B2 · kind B2 · utility
4Cited by
2References
1Claims
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Key dates
| Filing date | Nov 20, 2008 |
| Grant date | Oct 12, 2010 |
| Priority date | — |
| Expiry date | Dec 3, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement and method support instruction target history based register address indexing, whereby register addresses to be used by an instruction are decoded using a target history table of previous target register addresses, and an index into the target history table supplied by an index value in the instruction. An instruction may include at least one index value that identifies a previously used register address. During execution of the instruction, the index is retrieved from the instruction, and then a register address is retrieved from the target history table using the index.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.