Selective deposition of amorphous silicon films on metal gates
US7816218B2 · kind B2 · utility
5Cited by
4References
25Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 14, 2008 |
| Grant date | Oct 19, 2010 |
| Priority date | — |
| Expiry date | Dec 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic device includes a metal gate with a metal gate upper surface. The metal gate is disposed in an interlayer dielectric first layer. The interlayer dielectric first layer also has an upper surface that is coplanar with the metal gate upper surface. A dielectric etch stop layer is disposed on the metal gate upper surface but not on the interlayer dielectric first layer upper surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.