Methods for forming contacts for dual stress liner CMOS semiconductor devices
US7816271B2 · kind B2 · utility
5Cited by
3References
18Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jul 14, 2007 |
| Grant date | Oct 19, 2010 |
| Priority date | — |
| Expiry date | Oct 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0167
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor fabrication methods to forma of via contacts in DSL (dual stress liner) semiconductor devices are provided, in which improved etching process flows are implemented to enable etching of via contact openings through overlapped and non-overlapped regions of the dual stress liner structure to expose underlying salicided contacts and other device contacts, while mitigating or eliminating defect mechanisms such as over etching of contact regions underlying non-overlapped regions of the DSL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.