Gate patterning of nano-channel devices
US7816275B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2009 |
| Grant date | Oct 19, 2010 |
| Priority date | — |
| Expiry date | Apr 3, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/938
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.