Multi-die IC package and manufacturing method
US7816775B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2005 |
| Grant date | Oct 19, 2010 |
| Priority date | — |
| Expiry date | Dec 22, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for of manufacturing integrated circuit packages and a multi-chip integrated circuit package are disclosed. According to the method, a first die is attached onto a first side of a set of leads of a leadframe, and an adhesive is applied onto the set of leads at a second side opposite to the first side. A second die is attached onto the adhesive. The adhesive fills into the gaps defined by the set of leads. The adhesive is thereafter cured. In a multi-chip integrated circuit package made according to the method, the adhesive attaching the second die fills the gaps between the leads so that to avoid formation of internal cavities of the package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.