Integrated circuit arrangement with capacitor and fabrication method

US7820505B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Ralf Brederlow · Poing, DE
• Jessica Hartwich · Neubiberg, DE
• Christian Pacha · Birkenfeld, DE
• Wolfgang Rosner · Hersbruck, DE
• Thomas Schulz · Austin, US

Key dates

• Filing date: Sep 27, 2007
• Grant date: Oct 26, 2010
• Expiry date: Apr 1, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/80

Abstract

An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.