Semiconductor package with mechanical stress isolation of semiconductor die subassembly
US7821117B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2008 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Aug 22, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package (20) includes an organic substrate (24) and a semiconductor die subassembly (22). A method (50) for making the semiconductor package (20) entails providing (52) the organic substrate (24) having an opening (26) and electrical contacts (36). The subassembly (22) is formed by producing (64) a semiconductor die (28) and bonding it to a platform layer (30). An elastomeric adhesive (38) is utilized (92) to secure the subassembly (22) in the opening (26). Electrical interconnects (32) are provided (106) between the semiconductor die (28) and the electrical contacts (36) of the organic substrate (24). The organic substrate (24), semiconductor die (28), elastomeric adhesive (38), and electrical interconnects (32) are encapsulated (114) in a packaging material (46). The elastomeric adhesive (38) provides mechanical anchoring of the subassembly (22) to the substrate (24) and provides mechanical stress isolation of the semiconductor die (28) within the semiconductor package (20).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.