Multi-phase programming of multi-level memory
US7821840B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2008 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Apr 21, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and devices that facilitate multi-phase programming of data in a memory component are presented. Received data is programmed to a memory using multiple programming phases based on a predefined program pattern. A program learn is performed by varying drain voltages, as desired, to facilitate determining respective drain voltages related to specified subgroups associated with respective data levels for a first programming phase. A first programming phase is performed using learned drain voltages as initial drain voltages where drain voltage levels are varied during each program pulse to facilitate programming memory cells to respective intrinsic verify voltage levels based on respective data levels. A second programming phase is performed using ending drain voltages from the first programming phase as initial drain voltages where gate voltage levels are varied during each program pulse to facilitate programming memory cells to respective final verify voltage levels based on respective data levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.