Variable performance ranking and modification in design for manufacturability of circuits
US7823106B2 · kind B2 · utility
25Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2008 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Jan 2, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, computer system and program product introduce adding a variable performance ranking parameter to a diagram of a circuit to drive implementation of modifications that are yield improving, performance boosting, or performance-neutral. The information is paired to accomplish a more complete design for manufacturability modification in the design of circuits implemented on chips. In this matter, both yield and chip performance are improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.