Completely decoupled high voltage and low voltage transistor manufacturing processes
US7824977B2 · kind B2 · utility
5Cited by
2References
3Claims
0Family size
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Key dates
| Filing date | Mar 27, 2007 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | Aug 5, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A semiconductor wafer includes at least a partially manufactured high voltage transistor covered by a high-voltage low voltage decoupling layer and at least a partially manufactured low voltage transistor with the high-voltage low-voltage decoupling layer etched off for further performance of a low-voltage manufacturing process thereon. The high-voltage low-voltage decoupling layer comprising a high temperature oxide (HTO) oxide layer of about 30-150 Angstroms and a low-pressure chemical vapor deposition (LPCVD) nitride layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.