Sung-Shan Tai
44Patents
10h-index
28Co-inventors
71Inventor score
Filing activity: Apr 16, 1999 → Apr 27, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6509233B2 | Method of making trench-gated MOSFET having cesium gate oxide layer | Electricity | 35 | Expired |
| US6277695A | Method of forming vertical planar DMOSFET with self-aligned contact | Electricity | 33 | Expired |
| US7256446B2 | One time programmable memory cell | Electricity | 24 | Expired |
| US8394702B2 | Method for making dual gate oxide trench MOSFET with channel stop using three or four masks process | Electricity | 20 | Active |
| US8252647B2 | Fabrication of trench DMOS device having thick bottom shielding oxide | Electricity | 18 | Active |
| US8907416B2 | Dual gate oxide trench MOSFET with channel stop trench | Electricity | 16 | Active |
| US8334566B2 | Semiconductor power device having shielding electrode for improving breakdown voltage | Electricity | 14 | Active |
| US8187939B2 | Direct contact in trench with three-mask shield gate process | Electricity | 13 | Active |
| US9214545B2 | Dual gate oxide trench MOSFET with channel stop trench | Electricity | 13 | Active |
| US7667264B2 | Shallow source MOSFET | Electricity | 11 | Expired |
| US7875541B2 | Shallow source MOSFET | Electricity | 10 | Active |
| US8748268B1 | Method of making MOSFET integrated with schottky diode with simplified one-time top-contact trench etching | Electricity | 10 | Active |
| US9337329B2 | Method of fabrication and device configuration of asymmetrical DMOSFET with schottky barrier source | Electricity | 9 | Active |
| US9006053B2 | Method of making MOSFET integrated with schottky diode with simplified one-time top-contact trench etching | Electricity | 8 | Active |
| US8053315B2 | Method to manufacture split gate with high density plasma oxide layer as inter-polysilicon insulation layer | Electricity | 8 | Active |
| US9024378B2 | Device structure and manufacturing method using HDP deposited source-body implant block | Electricity | 7 | Active |
| US8372708B2 | Device structure and manufacturing method using HDP deposited using deposited source-body implant block | Electricity | 7 | Active |
| US8035159B2 | Device structure and manufacturing method using HDP deposited source-body implant block | Electricity | 6 | Active |
| US8048775B2 | Process of forming ultra thin wafers having an edge support ring | Emerging Cross-Sectional Technologies | 5 | Active |
| US8058687B2 | Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET | Electricity | 5 | Active |
| US7824977B2 | Completely decoupled high voltage and low voltage transistor manufacturing processes | Electricity | 5 | Active |
| US7855422B2 | Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process | Emerging Cross-Sectional Technologies | 5 | Active |
| US9000514B2 | Fabrication of trench DMOS device having thick bottom shielding oxide | Electricity | 5 | Active |
| US7932148B2 | Processes for manufacturing MOSFET devices with excessive round-hole shielded gate trench (SGT) | Electricity | 4 | Active |
| US7492005B2 | Excessive round-hole shielded gate trench (SGT) MOSFET devices and manufacturing processes | Electricity | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.