Three terminal nonvolatile memory device with vertical gated diode
US7825455B2 · kind B2 · utility
44Cited by
219References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 23, 2009 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | Jan 23, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.