Semiconductor package and method therefor
US7825505B2 · kind B2 · utility
0Cited by
5References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2009 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | Nov 11, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a semiconductor package is formed to include a tamper barrier that is positioned between at least a portion of the connection terminals of the semiconductor package and an edge of the semiconductor package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.