Method of making a semiconductor memory array of floating gate memory cells with program/erase and select gates
US7829404B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2007 |
| Grant date | Nov 9, 2010 |
| Priority date | — |
| Expiry date | Dec 4, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0433
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device, and method of making and operating the same, including a substrate of semiconductor material of a first conductivity type, first and second spaced apart regions in the substrate of a second conductivity type with a channel region therebetween, an electrically conductive floating gate having a first portion disposed over and insulated from the channel region and a second portion disposed over and insulated from the first region and including a sharpened edge, an electrically conductive P/E gate having a first portion disposed over and insulated from the first region and a second portion extending up and over the floating gate second portion and insulated therefrom by a first layer of insulation material, and an electrically conductive select gate having a first portion disposed laterally adjacent to the floating gate and disposed over and insulated from the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.