Method for eliminating a mask layer during thin film resistor manufacturing
US7829428B1 · kind B1 · utility
4Cited by
42References
20Claims
0Family size
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Key dates
| Filing date | Aug 26, 2008 |
| Grant date | Nov 9, 2010 |
| Priority date | — |
| Expiry date | Sep 13, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/47
Abstract
A method is disclosed for eliminating a mask layer during the manufacture of thin film resistor circuits. The method of the present invention enables the simultaneous etching of both deep vias and shallow vias using one mask layer instead of two mask layers. A high selectivity film layer of silicon nitride is formed on the ends of a thin film resistor layer. The thickness of the silicon nitride causes the etch time for a shallow via to the thin film resistor to be approximately equal to an etch time for a deep via that is etched through dielectric material to an underlying patterned metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.