Process for regeneration of a layer transferred wafer and regenerated layer transferred wafer
US7829436B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2006 |
| Grant date | Nov 9, 2010 |
| Priority date | — |
| Expiry date | Sep 8, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76254
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A processing time required for regeneration of a layer transferred wafer is reduced and the regeneration cost is lowered, while a removal amount at the regeneration is decreased the number of regeneration times is increased. A main surface of a semiconductor wafer (13) has a main flat portion (13d) and a chamfered portion (13c) formed in the periphery of the main flat portion (13d), an ion implanted area (13b) is formed by implanting ions only into the main flat portion (13d), a laminated body (16) is formed by laminating the main flat portion (13d) on a main surface of a support wafer (14), and moreover, the semiconductor wafer (13) is separated from a thin layer (17) in the ion implanted area (13b) by heat treatment at a predetermined temperature so as to obtain a thick layer transferred wafer (12), which is to be regenerated. The main flat portion (13d) of the semiconductor wafer (13) is formed to have a ring-shape step (13e) protruding from the chamfered portion (13c), and the semiconductor wafer (13) is separated from the thin layer (17) on the whole surface of the ion implanted area (13b) so that no step is generated in the periphery thereby to obtain the layer transferred wa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.