Transistor with a germanium-based channel encased by a gate electrode and method for producing one such transistor
US7829916B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2006 |
| Grant date | Nov 9, 2010 |
| Priority date | — |
| Expiry date | Mar 11, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6735
Abstract
Source and drain electrodes are each formed by an alternation of first and second layers made from a germanium and silicon compound. The first layers have a germanium concentration comprised between 0% and 10% and the second layers have a germanium concentration comprised between 10% and 50%. At least one channel connects two second layers respectively of the source electrode and drain electrode. The method comprises etching of source and drain zones, connected by a narrow zone, in a stack of layers. Then superficial thermal oxidation of said stack is performed so a to oxidize the silicon of the germanium and silicon compound having a germanium concentration comprised between 10% and 50% and to condense the germanium Ge. The oxidized silicon of the narrow zone is removed and a gate dielectric and a gate are deposited on the condensed germanium of the narrow zone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.