Split charge storage node inner spacer process

US7829936B2 · kind B2 · utility

Assignee

• Spansion LLC. · US

Inventors

• Minghao Shen · Road Town, VG
• Shenqing Fang · Fremont, US
• Wai Lo · Sha Tin, CN
• Christie Marrian · San Jose, US
• Chungho Lee · Sunnyvale, US
• Ning Cheng · San Jose, US
• Fred Cheung · San Jose, US
• Huaqiang Wu · Nanhu, CN

Key dates

• Filing date: Oct 17, 2007
• Grant date: Nov 9, 2010
• Expiry date: Mar 11, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/037

Abstract

Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing exposed portions of a first poly layer while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing exposed portions of a charge storage layer while leaving portions of the charge storage layer protected by the two split sub-lithographic first poly gates, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.