Fred Cheung
21Patents
11h-index
40Co-inventors
71Inventor score
Filing activity: Apr 23, 2001 → Sep 20, 2013
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6642573B1 | Use of high-K dielectric material in modified ONO structure for semiconductor devices | Emerging Cross-Sectional Technologies | 174 | Expired |
| US6451641B1 | Non-reducing process for deposition of polysilicon gate electrode over high-K gate dielectric material | Electricity | 110 | Expired |
| US6750066B1 | Precision high-K intergate dielectric layer | Electricity | 83 | Expired |
| US6740605B1 | Process for reducing hydrogen contamination in dielectric materials in memory devices | Electricity | 83 | Expired |
| US6630383B1 | Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer | Electricity | 46 | Expired |
| US7033957B1 | ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices | Emerging Cross-Sectional Technologies | 42 | Expired |
| US6949481B1 | Process for fabrication of spacer layer with reduced hydrogen content in semiconductor device | Electricity | 33 | Expired |
| US6794764B1 | Charge-trapping memory arrays resistant to damage from contact hole information | Emerging Cross-Sectional Technologies | 27 | Expired |
| US7163860B1 | Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device | Emerging Cross-Sectional Technologies | 17 | Expired |
| US6514844B1 | Sidewall treatment for low dielectric constant (low K) materials by ion implantation | Electricity | 13 | Expired |
| US6610594B2 | Locally increasing sidewall density by ion implantation | Electricity | 11 | Expired |
| US6735123B1 | High density dual bit flash memory cell with non planar structure | Emerging Cross-Sectional Technologies | 8 | Expired |
| US7732281B1 | Methods for fabricating dual bit flash memory devices | Electricity | 3 | Active |
| US7829936B2 | Split charge storage node inner spacer process | Electricity | 2 | Active |
| US8564042B2 | Dual storage node memory | Electricity | 1 | Active |
| US8486782B2 | Flash memory devices and methods for fabricating the same | Electricity | 1 | Active |
| US8329598B2 | Sacrificial nitride and gate replacement | Electricity | 0 | Active |
| US9461151B2 | Dual storage node memory | Electricity | 0 | Active |
| US7867848B2 | Methods for fabricating dual bit flash memory devices | Electricity | 0 | Active |
| US8748972B2 | Flash memory devices and methods for fabricating same | Electricity | 0 | Active |
| US7981745B2 | Sacrificial nitride and gate replacement | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.