Interconnect for chip level power distribution
US7829997B2 · kind B2 · utility
9Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2007 |
| Grant date | Nov 9, 2010 |
| Priority date | — |
| Expiry date | Mar 5, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device (601) is provided which comprises a substrate (603); a semiconductor device (605) disposed on said substrate and having a first major surface; a first metal strap (615) which is in electrical contact with said substrate and which is adapted to provide power to a first region (608) of said semiconductor device; and a second metal strap (616) which is in electrical contact with said substrate and which is adapted to provide ground to a second region (609) of said semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.