Dual stress memorization technique for CMOS application
US7834399B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2007 |
| Grant date | Nov 16, 2010 |
| Priority date | — |
| Expiry date | Jan 9, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0184
Abstract
A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.