High-k dual dielectric stack
US7834426B2 · kind B2 · utility
1Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2007 |
| Grant date | Nov 16, 2010 |
| Priority date | — |
| Expiry date | Jun 29, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a method including: providing a Group III-V component semiconductor material; forming a first layer over a surface of the Group III-V component semiconductor material, the first layer to unpin a Fermi level at the surface; forming a second layer over the first layer, the second layer for scaling an equivalent oxide thickness (EOT); and annealing the first layer before or after forming the second layer to remove bulk trap defects in the first layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.