Stack package having pattern die redistribution
US7834463B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2006 |
| Grant date | Nov 16, 2010 |
| Priority date | — |
| Expiry date | Oct 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stack package includes an edge-pad-type first semiconductor chip having bonding pads arranged near the edges thereof. A pattern die is placed on the first semiconductor chip. The pattern die is smaller in size than the first semiconductor chip and has line-type-redistribution parts formed thereon. An edge-pad-type second semiconductor chip smaller in size than the pattern die is placed on the pattern die. Bonding wires electrically connect the bonding pads of the first semiconductor chip and the redistribution parts of the pattern die and also electrically connect the redistribution parts of the pattern die and bonding pads of the second semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.