Reducing the fetch time of target instructions of a predicted taken branch instruction
US7836287B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2008 |
| Grant date | Nov 16, 2010 |
| Priority date | — |
| Expiry date | Nov 21, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.