Memory device and method
US7838342B2 · kind B2 · utility
1Cited by
16References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2008 |
| Grant date | Nov 23, 2010 |
| Priority date | — |
| Expiry date | Nov 28, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.