Method for forming a packaged semiconductor device
US7838420B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2007 |
| Grant date | Nov 23, 2010 |
| Priority date | — |
| Expiry date | Nov 8, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaged semiconductor device includes an interconnect layer over a first side of a polymer layer, a semiconductor device surrounded on at least three sides by the polymer layer and coupled to the interconnect layer, a first conductive element over a second side of the polymer layer, wherein the second side is opposite the first side, and a connector block within the polymer layer. The connector block has at least one electrical path extending from a first surface of the connector block to a second surface of the connector block. The at least one electrical path electrically couples the interconnect layer to the first conductive element. A method of forming the packaged semiconductor device is also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.