Semiconductor memory device having I/O unit
US7839709B2 · kind B2 · utility
4Cited by
3References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2007 |
| Grant date | Nov 23, 2010 |
| Priority date | — |
| Expiry date | Feb 10, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/1201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is capable of reducing a test time upon the same condition of the actual operation thereof. The semiconductor memory device includes an output data select unit and a data output unit. The output data select unit selectively outputs valid data, which are loaded on a plurality of global lines, in response to an output control signal activated after a delay time corresponding to an additive latency from entry of a read operation in a test mode. The data output unit aligns data outputted from the output data select unit and outputs the aligned data through data pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.