III-V MOSFET fabrication and device

US7842587B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Matthias Passlack · Overijse, BE
• Jonathan K. Abrokwah · Tempe, US
• Karthik Rajagopalan · Chandler, US
• Haiping Zhou · Bearsden, GB
• Richard J. Hill · Syracuse, US
• Xu Li · New Taipei, TW
• David Andrew James Moran · Glasgow, GB
• Iain G. Thayne · Milngavie, GB
• Peter Zurcher · Dripping Springs, US

Key dates

• Filing date: Jan 30, 2008
• Grant date: Nov 30, 2010
• Expiry date: Oct 21, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/85

Abstract

A semiconductor fabrication process includes forming a gate dielectric layer (120) overlying a substrate (101) that includes a III-V semiconductor compound. The gate dielectric layer is patterned to produce a gate dielectric structure (121) that has a substantially vertical sidewall (127), e.g., a slope of approximately 45° to 90°. A metal contact structure (130) is formed overlying the wafer substrate. The contact structure is laterally displaced from the gate dielectric structure sufficiently to define a gap (133) between the two. The wafer (100) is heat treated, which causes migration of at least one of the metal elements to form an alloy region (137) in the underlying wafer substrate. The alloy region underlies the contact structure and extends across all or a portion of the wafer substrate underlying the gap. An insulative or dielectric capping layer (140,150) is then formed overlying the wafer and covering the portion of the substrate exposed by the gap.