Stress-modified device structures, methods of fabricating such stress-modified device structures, and design structures for an integrated circuit

US7843039B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Edward C. Cooney, III · Jericho, US
• Mark D. Dupuis · South Burlington, US
• William J. Murphy · North Ferrisburgh, US
• Steven S. Williams · Longmont, US

Key dates

• Filing date: Feb 14, 2008
• Grant date: Nov 30, 2010
• Expiry date: Nov 26, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/62
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Stress-modified device structures, methods of fabricating such stress-modified device structures, and design structures for an integrated circuit. An electrical characteristic of semiconductor devices formed on a common substrate, such as the current gains of bipolar junction transistors, may be altered by modifying stresses in structures indirectly on or over, or otherwise indirectly coupled with, the semiconductor devices. The structures, which may be liners for contacts in a contact level of an interconnect, are physically spaced away from, and not in direct physical contact with, the respective semiconductor devices because at least one additional intervening material or structure is situated between the stress-imparting structures and the stress-modified devices. The intervening materials or structures, such as contacts extending through an insulating layer of a local interconnect level between the contact level and the semiconductor devices, provide paths for the transfer of stress from the stress-imparting structures to the stress-modified semiconductor devices.