Data latch with structural hold

US7843218B1 · kind B1 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Ravindraraj Ramaraju · Round Rock, US
• David R. Bearden · Austin, US
• Cody B. Croxton · Austin, US
• Prashant U. Kenkare · Austin, US

Key dates

• Filing date: Oct 28, 2009
• Grant date: Nov 30, 2010
• Expiry date: Oct 28, 2029

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318541
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A multiplexed data flip-flop circuit (500) is described in which a multiplexer (510) outputs functional or scan data, a master latch (520) generates a master latch output signal at a hold time under control of a master clock signal, a slave latch (540) generates a flip flop output signal at a launch time under control of a slave clock signal, clock generation circuitry (550) generates a second clock signal that has a DC state during a functional mode and has a switching state during a scan mode, and data propagation logic circuitry (564) uses the first and second clock signals to generate the master and slave clock signals during a scan mode to delay the launch time of the slave latch with respect to the hold time of the master latch.