Semiconductor memory device comprising sense amplifier having P-type sense amplifier and N-type sense amplifiers with different threshold voltages
US7843751B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2009 |
| Grant date | Nov 30, 2010 |
| Priority date | — |
| Expiry date | Jan 12, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.