Method to identify timing violations outside of manufacturing specification limits
US7844932B2 · kind B2 · utility
3Cited by
4References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2008 |
| Grant date | Nov 30, 2010 |
| Priority date | — |
| Expiry date | Feb 5, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of evaluating an integrated circuit design selects manufacturing parameters of interest which are outside of manufacturing specification limits. Then, the method runs timing tests on the integrated circuit design and successively evaluates the timing test results in an iterative process that considers the timing performance sensitivity to the selected manufacturing parameters of interest. The design is made more robust to each parameter out of manufacturing range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.