Patent · US Active

Flash memory array system including a top gate memory cell

US7848140B2 · kind B2 · utility

1Cited by

19References

20Claims

0Family size

Assignee

Silicon Storage Technology, Inc. · US

Inventors

Hieu Van Tran · San Jose, US
Hung Quoc Nguyen · Carrollton, US
Anh Ly · San Jose, US
Sheng-Hsiung Hsueh · San Jose, US
Sang Thanh Nguyen · Union City, US
Loc B. Hoang · San Jose, US
Steve Choi · Irvine, US
Thuan Vu · San Jose, US

Key dates

Filing date	Jul 22, 2009
Grant date	Dec 7, 2010
Priority date	—
Expiry date	Aug 17, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/832
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.