Memory circuit having reduced power consumption
US7848172B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2008 |
| Grant date | Dec 7, 2010 |
| Priority date | — |
| Expiry date | Feb 18, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit having reduced power consumption includes a plurality of memory sub-arrays and a shared circuit coupled to each of the memory sub-arrays. Each memory sub-array includes at least one row circuit, at least one column circuit, and a plurality of memory cells operatively coupled to the row and column circuits. The row and column circuits are operative to provide selective access to one or more of the memory cells. The shared circuit includes circuitry, external to the memory sub-arrays, which is operative to control one or more functions of the memory sub-arrays as a function of at least one control signal supplied to the memory circuit. The memory circuit is operative, with at least one of the memory sub-arrays operative, with one or more of the memory sub-arrays powered and concurrently with one or more of the memory sub-arrays unpowered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.