Patent · US Active

Formally deriving a minimal clock-gating scheme

US7849428B2 · kind B2 · utility

5Cited by

2References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Harry Barowski · Balingen, DE
J. Adam Butts · Hartsdale, US
Tobias Gemmeke · Santa Clara, US
Nicolas Maeding · Holzgerlingen, DE
Viresh Paruthi · Austin, US

Key dates

Filing date	Apr 23, 2008
Grant date	Dec 7, 2010
Priority date	—
Expiry date	Nov 25, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/06
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The present invention provides a fully automatic method for obtaining a circuit having minimized power consumption due to clock-gating. A circuit design to be optimized is modified to a reduced power modified design and associated with a clock gating scheme. Verification tools compare the modified design with the original design to a predetermined trigger-events to determine if the modified design can be used. Further modifications may be made iteratively until an optimal design is achieved.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.