Semiconductor device and process for improved etch control of strained silicon alloy trenches
US7851313B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2007 |
| Grant date | Dec 14, 2010 |
| Priority date | — |
| Expiry date | Jul 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor process for improved etch control in which an anisotropic selective etch is used to better control the shape and depth of trenches formed within a semiconductor material. The etchants exhibit preferential etching along at least one of the crystallographic directions, but exhibit an etch rate that is much slower in a second crystallographic direction. As such, one dimension of the etching process is time controlled, a second dimension of the etching process is self-aligned using sidewall spacers of the gate stack, and a third dimension of the etching process is inherently controlled by the selective etch phenomenon of the selective etchant along the second crystallographic direction. A deeper trench is implemented by first forming a lightly doped drain (LDD) region under the gate stack and using the sidewall spacers in combination with the LDD regions to deepen the trenches formed within the semiconductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.