System and method for shielding of package on package (PoP) assemblies
US7851894B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 23, 2008 |
| Grant date | Dec 14, 2010 |
| Priority date | — |
| Expiry date | Dec 23, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package has a first substrate having a plurality of metal traces. At least one die is electrically coupled to the first surface of the first substrate. A plurality of land pads is formed on the first surface of the first substrate. A mold compound encapsulates portions of the die and portions of the first surface of the first substrate. A conductive coating is applied to the mold compound and electrically coupled to at least one metal trace. A non-conductive coating is formed over the conductive coating and portions of the mold compound. A plurality of vias is formed through the non-conductive coating and the mold compound to expose the land pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.