Wafer level packaged MEMS integrated circuit

US7851925B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Horst Theuss · Wenzenbach, DE
• Markus Loehndorf · Munich, DE
• Florian Schoen · Altdorf, DE

Key dates

• Filing date: Sep 19, 2008
• Grant date: Dec 14, 2010
• Expiry date: Apr 23, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/16235
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A wafer-level packaged integrated circuit includes a semiconductor substrate including a first silicon layer. A micro-electromechanical system (MEMS) device is integrated into the first silicon layer. A thin-film deposited sealing member is deposited over the first silicon layer and is configured to seal a cavity in the first silicon layer. At least one additional layer is formed over the sealing member. At least one under bump metallization (UBM) is formed over the at least one additional layer.