Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructions
US7853777B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2005 |
| Grant date | Dec 14, 2010 |
| Priority date | — |
| Expiry date | Feb 8, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for reducing instruction re-fetching in a multithreading processor configured to concurrently execute a plurality of threads is disclosed. The apparatus includes a buffer for each thread that stores fetched instructions of the thread, having an indicator for indicating which of the fetched instructions in the buffer have already been dispatched for execution. An input for each thread indicates that one or more of the already-dispatched instructions in the buffer has been flushed from execution. Control logic for each thread updates the indicator to indicate the flushed instructions are no longer already-dispatched, in response to the input. This enables the processor to re-dispatch the flushed instructions from the buffer to avoid re-fetching the flushed instructions. In one embodiment, there are fewer buffers than threads, and they are dynamically allocatable by the threads. In one embodiment, a single integrated buffer is shared by all the threads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.