Layer transfer process and functionally enhanced integrated circuits produced thereby
US7855101B2 · kind B2 · utility
299Cited by
24References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2009 |
| Grant date | Dec 21, 2010 |
| Priority date | — |
| Expiry date | Aug 20, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure for a semiconductor components is provided having a device layer sandwiched on both sides by other active, passive, and interconnecting components. A wafer-level layer transfer process is used to create this planar (2D) IC structure with added functional enhancements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.