Field effect transistor and method of fabricating same
US7855110B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2008 |
| Grant date | Dec 21, 2010 |
| Priority date | — |
| Expiry date | Aug 6, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An FET and method of fabricating an FET. The method includes forming a gate dielectric layer on a top surface of a silicon region of a substrate and forming a gate electrode on a top surface of the gate dielectric layer; forming a source and a drain in the silicon region and separated by a channel region under the gate electrode, the source having a source extension extending under the gate electrode and the drain having a drain extension extending under the gate electrode, the source, source extension, drain and drain extension doped a first type; and forming a source delta region contained entirely within the source and forming a drain delta region contained entirely within the drain, the delta source region and the delta drain region doped a second dopant type, the second dopant type opposite from the first dopant type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.