Lock and key through-via method for wafer level 3 D integration and structures produced
US7855455B2 · kind B2 · utility
28Cited by
16References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 26, 2008 |
| Grant date | Dec 21, 2010 |
| Priority date | — |
| Expiry date | Sep 26, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.