Treatment method of semiconductor, method for manufacturing MOS, and MOS structure
US7858529B2 · kind B2 · utility
0Cited by
2References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2006 |
| Grant date | Dec 28, 2010 |
| Priority date | — |
| Expiry date | Jun 7, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/125
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The method of the present invention includes providing a semiconductor substrate with a recess; performing a pre-cleaning step on the semiconductor substrate; and performing a first reduction step, a lateral etching step and a second reduction step on the semiconductor substrate. The MOS structure includes a semiconductor substrate, a gate structure on the semiconductor substrate, a pair of recesses with beak sections extending to and under the gate structure, and a strain material filling the recess. The recess inside the semiconductor substrate processed by the method including the lateral etching step forms a beak section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.