Multi-layer stacked wafer level semiconductor package module
US7859102B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2008 |
| Grant date | Dec 28, 2010 |
| Priority date | — |
| Expiry date | Jul 5, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked wafer level semiconductor package module includes a semiconductor chip module including first and second semiconductor chips each having a rectangular shape. The first semiconductor chip has first pads disposed along a first short side of a lower surface thereof. The second semiconductor chip has second pads disposed along a first short side of a lower surface thereof. The first and second semiconductor chips are stacked so as to expose the first pad and the second pad on one side of the stacked first and second semiconductor chips. The package also includes a substrate having a first connection pad facing the first pad and a second connection pad facing the second pad. The package also includes a first connection member for connecting the first pad to the first connection pad, and a second connection member for connecting the second pad to the second connection pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.