Method of forming CMOS transistors with dual-metal silicide formed through the contact openings
US7861406B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2007 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Jan 21, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49156
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and associated structures of forming a microelectronic device are described. Those methods may include amorphizing at least one contact area of a source/drain region of a transistor structure by implanting through at least one contact opening, forming a first layer of metal on the at least one contact area, forming a second layer of metal on the first layer of metal, selectively etching a portion of the second metal layer, annealing the at least one contact area to form at least one silicide, and removing the unreacted first metal layer and second metal layer from the transistor structure and forming a conductive material in the at least one contact opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.