Low cost bumping and bonding method for stacked die
US7863092B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2008 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Jan 6, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of fabricating an integrated circuit assembly in which a plurality of mother dice having a plurality of through-die vias (TDVs) are formed in the first (active) surface of a semiconductor wafer, a substrate is attached to the active surface of the wafer, the second (inactive) surface is back-ground to expose one end of the through-die vias, a plurality of daughter dice are mounted to the inactive surface of the wafer, each daughter die being electrically coupled to a mother die, and the mother dice are then singulated. Attaching the substrate can be accomplished by adhering a glass wafer carrier to the wafer. The wafer carrier allows handling of the wafer during back-grinding the inactive surface, forming under-bump metal (UBM) pads on the TDVs and attaching the daughter dice.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.