Direct contact between high-κ/metal gate and wiring process flow
US7863123B2 · kind B2 · utility
3Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2009 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Jan 19, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A low resistance contact is formed to a metal gate or a transistor including a High-κ gate dielectric in a high integration density integrated circuit by applying a liner over a gate stack, applying a fill material between the gate stacks, planarizing the fill material to support high-resolution lithography, etching the fill material and the liner selectively to each other to form vias and filling the vias with a metal, metal alloy or conductive metal compound such as titanium nitride.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.