High performance chip carrier substrate
US7863526B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2008 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Jan 21, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/4916
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, remaining signal pads are moved closer to the edge of the chip footprint. At the voltage layer below the first fanout layer, the remaining signal pads are moved again, closer to the edge of the chip footprint. In the second fanout layer, below the voltage layer, the remaining signal pads escape. The region where signal pads are moved provides increased space for power PTHs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.